Rockwell-automation FlexPak 3000 Power Module SW-Version 4.3 Bedienungsanleitung Seite 176

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Seitenansicht 175
APPENDIX D
FlexPak 3000 49’1340 e
D-6
From Speed Reference
Mode Select Block Diagram
(SPD LOOP REFERENCE)
SPD LOOP PI PROP GAIN
(SPD LOOP ERROR)
(SPD LOOP FEEDBACK)
To CML Reference
Block Diagram
To CML Reference
Block Diagram
*ARMATURE VOLT
DC TACH
AC TACH
PULSE TACH
FEEDBACK
SELECT
(ANALOG TACH FEEDBACK)
(PULSE TACH
FEEDBACK)
SPD LEADLAG LOW FREQ
SPD LEADLAG RATIO
* = Default Selection
LEAD/LAG
or
LAG/LEAD
WLD
WRATIO
MOTOR RATED
ARM VOLTS
ARM VOLTAGE
GAIN ADJ
ARM VOLTAGE
ZERO ADJ
(ARMATURE VOLTAGE)
SOFTWARE SCALING
A/D
Armature
Voltage
(internal)
(CML FEEDBACK)
8 sample average
SOFTWARE
SCALING
IR COMPENSATION
(IR COMPENSATION TP)
ANALOG TACH
ZERO ADJ
ANALOG TACH
GAIN ADJ
ANLG TACH
VOLTS/1000
SOFTWARE SCALING
Analog Tachometer
(+ hi) terminal 21
(+ lo) terminal 22
(COM) terminal 23
Pulse Tachometer
(from optional
pulse tach kit)
+
-
A/D
TOP SPEED
SOFTWARE SCALING
F/D
PULSE TACH PPR PULSE TACH QUADRATURE
+
D
.
5
(
E
)
P
.
2
9
5
P
.
2
9
7
D
.
9
(
A
)
D
.
9
(
B
)
P
.
2
1
1
P.009
P
.
2
0
4
P
.
2
0
5
P
.
2
0
1
P
.
2
9
0
P
.
2
0
3
P
.
0
1
1
P
.
2
0
7
P
.
2
0
8
P
.
2
9
2
P
.
2
9
1
P
.
2
0
2
P
.
2
9
0
P
.
2
8
9
P
.
2
0
0
P
.
2
1
4
P
.
2
1
3
*ZERO
SPD LOOP PI INIT VAL
ANALOG MANUAL TRIM REF
SPD LOOP PI INIT SEL
1)
Netw. Drop 2, Reg. 32
To CML Reference
Block Diagram
SPD LOOP
PI LEAD FREQ
NEGATIVE
CURRENT LIM
ANALOG IN 2
NETW IN REG 1, 2, 3
From Network
From I/O Expansion
Inputs Block Diagram
{
NEG CURRENT
LIM SEL
*REGISTER
ANALOG IN 1
EN
P
.
2
1
2
D
.
1
3
P
.
0
0
6
D
.
9
(
C
)
P
.
2
2
4
(A)
(B)
POSITIVE CURRENT LIM
POS CURRENT
LIM SEL
*REGISTER
ANALOG IN 1
ANALOG IN 2
NETW IN REG 1, 2, 3
From Network
From I/O Expansion
Inputs Block Diagram
{
P
.
0
0
5
D
.
1
3
P
.
2
2
3
(B)
(A)
Network Drop 1, Reg. 39
D.4 ANALOG MAN TRIM REF
P.194
MUL
IN
A * B
1000
UNDERWIND ENABLE 1)
Netw. Drop 1, Reg. 32, Bit 5
SPEED FEEDBACK GAIN 1)
Netw. Drop 1, Reg. 38
P
.
2
9
6
D
.
1
4
(
D
)
T
o
L
e
v
e
l
D
e
t
e
c
t
o
r
s
.Netw.Drop 1, Reg. 32, Bit 6
0
(SPD LOOP OUTPUT)
PI
KP
HI
WLD LO
P
.
2
9
9
INIT
RST
* BYPASS
LEAD/LAG
LAG/LEAD
SPD LEADLAG
SELECT
P
.
2
1
6
KEYPAD,
TERMBLK
or SERIAL
SPD LOOP LAG FREQ
SPD LOOP
LAG BYPASS
WLG
LAG
(SPD LOOP
LAG OUTPUT)
P
.
2
1
5
P
.
2
1
7
P
.
2
9
8
OFF
*ON
Off
OR
Internal Sequencing
(drive stopped)
(Other)
NETWORK
P.000 CSS
SPD LOOP PI RESET
EN
NOTE 1) Network only register. CSS must be set to NETWORK
and NETW REGISTER MAP SEL = ALTERNATE
NOTE 3) Also enables/disables on inverter CML ref. block diagram.
NEG CURRENT LIM INV EN 3)
P
.
2
2
6
SPD LOOP CUR LIM
OUT
NETWORK
P.000 CSS
Figure D.6 - Speed Loop
Seitenansicht 175
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